CRST Register Specification Tool
CRST is a register specification and change management tool. Manual
definition of register specifications is time consuming and error-prone.
Specification changes introduce further delays and increase the probability
of errors due to the need for rewriting Verilog code and redoing documentation.
Propagation of changes is hard to track manually.
CRST aids design implementation by automating the specification of registers.
It automatically generates the necessary synthesizable Verilog code,
verification definitions that plug into Fiesta® Open Verification
Environment, C headers and documentation, dramatically speeding up design,
verification, software development cycles and updating documentation,
all at one go. The tool automatically propagates specification changes
to all generated outputs, ensuring consistency, and further reducing
the possibility of errors.
will start using the tool during the micro-architecture and design phase.
Changes can be easily made to the registers, with all outputs automatically
regenerated. Device driver development can start as soon as the first
cut register specification is done, allowing for early feedback loops.
Intuitive Graphical User Interface promotes easy adoption and integration
into design cycle
input validations reduce errors
generation and regeneration of directly synthesizable Verilog code
dramatically compresses design cycle
generation and regeneration of design document reduces time spent
generation and regeneration of C headers reduces software development
generation and regeneration of register information useful for verification
reduces verification time (in Tcl for Comit Fiesta® CVXT Open
Verification Environment, or a parse-able text file)
integration into version control and release management tools like
cvs and make supports version-compares
Write-once Use-many bus interface library scheme helps build repository
of reusable interface definitions
Intuitive Graphical User Interface
options to define a variety of bus interface libraries
interface library reusability
Verilog code suitable for synthesis and simulation
documentation output: customizable heading levels and options suitable
for inclusion into MS-Word documents
instantiation templates for generated modules
design rule checks for automatic, early detection of specification
filling for unused portions of registers
documentation facilitates good design practice
format directly compatible with version control and release management
based specifications for registers
bank with registers, Instantiation Template, Definitions (`defines)
for easy use in other verilog sources: Verilog
file definitions for each register and each bitfield - used for
diagnostic software, and device driver development: C
definitions, for Comit Fiesta® CVXT, automated register read
write, power up and reset tests: Tcl
/ 2.8 (7/8)
7.1 / 7.2
/ 98 / 2000/ XP
Copyright Comit Systems, Inc. Fiesta is a registered trademark of Comit
Systems, Inc. CACT, CWGT, CRST, CSMT, CVXT, CMMT, CSGT and CMBT are trademarks
of Comit Systems, Inc. All other trademarks acknowledged as property of
their respective trademark holders.
toolkit proven at Comit