System Architecture Capture Tool
CACT is a VLSI design tool for architecture definition, structural design
and code generation. Its graphical editor allows designers to input
block level architecture, including third party IP, and generate an
implementation roadmap for all modules and interfaces. The tool saves
time by allowing rapid and easy definition of architectural blocks and
automatically generating Verilog® and VHDL code and documentation.
The Graphical User Interface (GUI) lets users add blocks in a hierarchical
manner. CACT also generates system and module level block diagrams with
the ability to automatically connect signals by name. CACT also makes
drawing block diagrams a breeze.
Intuitive Graphical User Interface speeds adoption
use graphical input or existing code as starting point
HDL code, professional diagrams and organized documentation
overhead by integrating directly with version control / release management
design debug time by automatically embedding entity descriptions in
explanation and understanding time, especially for code reviews, for
code maintenance and transfer of technology
consistency between documentation and code
redundant information entry.
to use Graphical User Interface enables definition of connectivity
as well as properties and comments for design elements
definitions enable non-cluttered schematics, even at ASIC top levels
HDL code, and infers connectivity and hierarchy information, making
it easy to use the tool for existing code and for third party IP
generates fully commented Verilog® or VHDL code. Comments include
connectivity information, making debug easier
generates professional looking vectored diagrams in Postscript and
WindowsTM Metafile formats, including complete MS-Word® documentation
including inline diagrams
generates pin tables in generated documentation, reducing redundancy
in user input
database makes it easy to integrate database into version control/release
management tools like cvs and Perforce.
of Verilog® code
code for modules
diagram: .PS, .WMF
and Tables: .HTML, .RTF
Documentation in MS-Word format.
/ 2.8 (7/8)
7.1 / 7.2
/ 98 / 2000 / XP
Copyright Comit Systems, Inc. Fiesta is a registered trademark of Comit
Systems, Inc. CACT, CWGT, CRST, CSMT, CVXT, CMMT, CSGT and CMBT are trademarks
of Comit Systems, Inc. All other trademarks acknowledged as property of
their respective trademark holders.
tool proven at Comit
input of block level
block diagrams easy