Physical Design

Comit offers complete front to backend services from specs to GDSII.

Complete back-end physical design services offer a full heiarchical flow including Place & Route, Clock Tree Synthesis, Crosstalk / Signal Integrity, DRC and LVS.

   Complete Specs to GDSII

   Process geometries
   down to 90 nanometer

   Full hierarchical flow  
   
   Target foundries:
   - Agere
   - Lucent
   - NEC
   - OKI Semi
   - TSMC
   - UMC

   "Comit's ASIC designs are
    so DRC clean that OKI
    actually is able to discount
    mask NRE charges to our
    customers if the design
    comes from Comit."

             - Mo Ibrahim
              Director of Strategic               Account Sales
              OKI Semiconductor

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SoC DESIGN

SoC VERIFICATION

IP INTEGRATION

CHIP DESIGN FLOW AND TOOLS

FPGA DESIGN

PHYSICAL DESIGN

ALLIANCE PARTNERS

RISK MANAGEMENT

Comit has taped out multi million gate ASICs with multiple clock domains. Recent designs are targeted to cutting edge 130nm processes in Low Voltage Fluro-Silicate-Glass and LV OD.

Comit's knowledge of front-end RTL design as well as back-end physical layout ensures tight coupling in concurrent RTL physical design strategies. Comit's experience in multi-million gate hierarchical design with industry standard design tools ensures early management of pitfalls such as channel routing and horizon effects.

ASIC Layout Services
Starting with a gate level netlist handoff, generate and insert:
- TAP Controllers
- Boundary scan

Generate:
- IOLIOH vectors
- DC parametrics
- Connectivity tests for multiple dies in a package

Generate ASIC top level including
- I/O Muxes
- Pad ring

Generate Scripts for
- die layout tools
- packaging and test tools

Perform:
- Floorplanning
- Power & Ground Strap generation and placement
- Automatic & Manual I/O Placement
- Clock tree synthesis
- Place & Route
- Parasitic extraction
- Timing closure
- DRC
- LVS
- Crosstalk

Comit's experience with a variety of silicon vendors virtually guarantees your designs will work first time.  Comit has targeted designs to Agere, Lucent, NEC, OKI, TSMC and UMC. Familiarity with silicon vendor process design kits and third-party libraries, and knowledge of foundry sign off parameters including foundry-preferred layer mapping tables and verification grids, metal coverage rule and antenna rule checks, and knowledge of specific process parameters relating to RC extraction etc. minimizes your risk, and has contributed to Comit's unbroken record of first silicon success.

Knowledge of Reticle Enhancement Techniques (RET) such as optical and process correction, phase-shift mask, scattering bars and off-axis illumination ensures that Comit can work with your silicon vendor on physical verification of sub-wavelength designs.